12-bit a/d converter ad1671 asd0010777 rev. m information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent righ ts of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2017 analog devices, inc. all rights reserved. 1.0 scope this specification documents the detail requirement s for space qualified product manufactured on analog devices, inc.?s qml certified line per mil-prf- 38535 level v except as modified herein. the manufacturing flow described in the standard space level products program brochure is to be considered a part of this specificat ion. this brochure can be found at: http://www.analog.com/aerospace this data sheet specifically details the space grade version of this product. a more detailed operational description and a complete data sheet for co mmercial product grades can be found at www.analog.com/ad1671 . 2.0 part number. the complete part number(s) of this specification follow: part number description ad1671-703d 12-bit a/d converter ad1671-703f 12-bit a/d converter ad1671-713f 12-bit a/d converter with radiation test 2.1. case outline: letter descriptive designator case outline (lead finish per mil-prf-38535) d cdip2-t28 28-lead sidebrazed dip (.6") f cdfp3-f28 28-lead bottom-brazed flatpack figure 1 - terminal connections.
ad1671 asd0010777 rev. m | page 2 of 7 3.0 absolute maximum ratings. (t a = 25c, unless otherwise noted) v cc to acom.............................................................................................................-0.5v to + 6.5v v ee to acom.............................................................................................................-6.5v to + 0.5v v logic to dcom.........................................................................................................-0.5v to +6.5v acom to dcom........................................................................................................-1.0v to +1 .0v v cc to v logic ..............................................................................................................-6.5v to +6.5v encode to dcom....................................................................................................-0.5v to v logic +0.5v ref in, bpo/upo to acom ........... .........................................................................-0.5v to v cc +0.5v ain to acom.............................................................................................................-11v to +11v power dissipation ........... ................ ................... ................... .............. .................. ....1000mw operating temperature range...................................... ............................................-55c to +125c storage temperature range .................. .................. .................. ................ ...............-65c to +150c lead temperature (soldering, 60 sec.) ........................ .................. ............... ...........+300c junction temperature (t j ).........................................................................................+150c 3.1. thermal characteristics: thermal resistance, sbdip (d) package junction-to-case ( jc ) = 28c/w max junction-to-ambient ( ja ) = 60c/w max thermal resistance, bottom brazed (f) package junction-to-case ( jc ) = 22c/w max junction-to-ambient ( ja ) = 60c/w max figure 2. functional block diagram
ad1671 asd0010777 rev. m | page 3 of 7 4.0 electric table: table i parameter symbol conditions sub- limit limit units see notes at end of table note 1/ group min max resolution res 1, 2, 3 12 bits integral nonlinearity inl all codes histogram 1 -2.5 2.5 lsb 2, 3 -3 3 lsb differential nonlinearity +dnl all codes histogram 1, 2, 3 0 2 lsb -dnl -1 0 lsb unipolar offset error v ose 2.5v, 5v span 1 -9 9 lsb unipolar offset drift tc vos 2.5v, 5v span t a = -55oc, +125oc 2,3 20 ppm/ c gain error a e unipolar & bipolar 1 0.37 %fsr gain drift tc a unipolar & bipolar t a = -55oc, +125oc 2,3 40 ppm/ c bipolar zero error b poe 2.5v, 5v span 1 -10 10 lsb bipolar zero drift tc bpo 2.5v, 5v span t a = -55oc, +125oc 2,3 30 ppm/ c analog input ranges v in unipolar mode rin=10m 3/ 1,2,3 2.5 v rin=10k 3/ 1,2,3 5 bipolar mode rin=10m 3/ 1,2,3 2.5 rin=10k 3/ 1,2,3 5 reference voltage 4/ v ro unipolar & bipolar 2/ 1 2.475 2.525 v reference drift tc vro unipolar & bipolar 2/ t a = -55c, +125c 2,3 30 ppm/ c reference current i ref unipolar mode 2/ 1 2.5 ma bipolar mode 2/ 1 1 power dissipation p d v s = 5.25v, v logic = +5.5v 1,2,3 750 mw power supply current i cc tested under static conditions 1,2,3 75 ma i ee -75 i logic 5 psrr v cc full-scale change measured 1,2,3 -4 4 lsb v ee v logic input logic voltages v ih encode input 1,2,3 2.0 v v il 0.8 input logic current i ih 1,2,3 -10 10 a i il output logic voltage v oh i oh = 500a i ol = 1.6ma 1,2,3 2.4 v v ol 0.4 output logic current i oh 1,2,3 500 a i ol -1.6 ma signal to noise plus distortion sinad f in = 100khz, f s = 1mhz, -0.5 db input 4,5,6 68 db effective number of bits enob 4 11 bits total harmonic distortion thd 4,5,6 -73 db peak spurious of peak harmonic component ps 4,5,6 -75 intermodulation distortion 2 nd 2 nd order products 4,5,6 -75 3 rd 3 rd order products conversion time t conv see figure 3 9,10,11 800 ns sample rate fs 2/ 9,10,11 1.25 msps
ad1671 asd0010777 rev. m | page 4 of 7 table i (continued) table i notes: 1/ v cc = +5v, v ee = -5v, v logic = +5v, unless otherwise specified. 2/ this parameter is guaranteed, but not necessarily tested. 3/ r in values are typical values only. 4/ the ad1671 includes an onboard +2.5 v reference. the reference input pin (ref in) can be connected to reference output pin (ref out) or a standard external +2.5 v reference can be selected to meet specific system requirements. fast switching input dependent currents are modulated at the reference input. the reference input voltage can be held with the use of a capacitor. to prevent the ad1671?s onboard reference from oscillating when not connected to ref in, ref out must be connected to +5 v. it is possible to connect ref out to +5 v due to its output circuit implementation which shuts down the reference encode pulse high figure 3.timing diagrams parameter symbol condit ions sub- limit limit units see notes at end of table note 1/ group min max encode width high (short encode) t enc see figure 3 2/ 9,10,11 20 50 ns encode width low (long encode) t encl see figure 3 2/ 9,10,11 20 dav pulse width t dav see figure 3 9,10,11 150 300 encode falling edge delay t f see figure 3 2/ 90 start new conversion delay t r see figure 3 2/ 90 data and qtr delay from dav falling edge t dd see figure 3 2/ 9 20 data and otr delay from dav rising edge t ss see figure 3 2/ 9 20
ad1671 asd0010777 rev. m | page 5 of 7 encode pulse low figure 3.timing diagram. 4.1. electrical test requirements: 1/ pda applies to subgroup 1 only. deltas excluded from pda. 2/ see table iii for delta parameters. table ii test requirements subgroups (in accordance with mil- prf-38535, table iii) interim electrical parameters 1 final electrical parameters 1, 2, 3,4,5,6 9, 10, 11 1 / 2 / group a test requirements 1, 2, 3,4,5,6,9, 10, 11 group c end-point electrical parameters 1 2 / group d end-point electrical parameters 1 group e end-point elec trical parameters 1
ad1671 asd0010777 rev. m | page 6 of 7 4.2. table iii. lifetest / burn-in delta limits. table iii test title burn-in endpoint lifetest endpoint delta units i cc 75 75 7.5 ma max v oh 2.4 2.4 0.24 v min v ol 0.4 0.4 0.1 v max 5.0 life test/burn-in circuit: 5.1 htrb is not applicable for this drawing. 5.2 burn-in is per mil-std-883 method 1015, test condition b. 5.3 steady state life test is per mil-st d-883 method 1005, test condition b.
ad1671 asd0010777 rev. m | page 7 of 7 ? 2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the proper ty of their respective companies. printed in the u.s.a. 10/2017 rev description of change date a initiate feb. 29, 2000 b add flatpack. add radiation part number. excl ude deltas from pda. delete reference to unused subgroups in tabl e ii. update table iii. aug. 21, 2001 c update web address. feb. 14, 2002 d change table i ac parameters from subgroups 1, 2, 3 to subgroups 9, 10, 11. (sinad, thd, ps, 2nd and 3 rd ) jan. 9, 2003 e delete burn-in circuit aug. 5, 2003 f change tcvos, tca, tcbpo, tcvro from subgro ups 2, 3 to subgroup 8. add subgroup 8 to table ii. jun. 14, 2004 g update header/footer and add to 1.0 scope description. feb. 12, 2008 h add junction temperature (t j ).....+150c april 4, 2008 i change subgroup for enob to 9 aug. 3, 2009 j match dnl limits and units to actual production test plus this now confirms testing does ensure no missing codes. minor limit format change for tests with lsb. update document formatting sep. 15, 2011 k removed obsolete part number nov. 7, 2011 l add application note to prevent oscillation jan. 18, 2015 m corrected subgroup 8,9,10,11 to 2,3,4,5,6 ( t cvos, t ca, t cbpo, t cvro,sinad, thd, ps, 2nd and 3rd). add fs symbol for sample rate. oct. 06, 2017
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